The prior art includes TFET devices, which can be used as semiconductor switches. Conventional TFET devices take advantage of tunneling current between the source region and the channel region. The tunneling occurs under certain bias voltage conditions; otherwise, the TFET device functions as a reverse-biased diode. In this regard, FIG. 1 is a schematic cross sectional view of a conventional N-type TFET device 100. TFET device 100 includes a layer of semiconductor material 102, a source region 104, a drain region 106, and a gate structure 108. Most of semiconductor material 102 is lightly doped with an N-type impurity (N−). Source region 104, which is formed in semiconductor material 102, is highly doped with a P-type impurity (P+). Drain region 106, which is also formed in semiconductor material 102, is highly doped with an N-type impurity (N+). TFET device 100 includes a channel region 110 that is located between source region 104 and drain region 106. As shown in FIG. 1, channel region 110 is generally located below gate structure 108, as is well understood.
When used as a semiconductor switch device, TFET device 100 is biased such that the drain voltage (Vd) is higher than the source voltage (Vs). The gate voltage (Vg) is then controlled to turn the switch on or off. More specifically, if Vg is higher than the threshold voltage (Vt) of TFET device 100, then the switch turns on and source-to-drain current flows. If, however, Vg is less than Vt, then the switch remains off, TFET device 100 functions as a reverse-biased diode, and no current flows. FIG. 1 depicts a state where TFET device 100 is conducting source-to-drain current (Vs=0.0 volts; Vg=1.0 volts; Vd=1.0 volts). Under these bias conditions, electrons accumulate in channel region 110 near the upper surface of semiconductor material 102 and directly under gate structure 108. This accumulation of electrons in turn creates a very well defined and localized P+/N+ junction between source region 104 and channel region 110. This stiff P+/N+ junction represents a tunneling junction 112 for TFET device 100. Electrons and holes can easily pass or tunnel through tunneling junction 112, which results in high source-to-drain current.
A TFET device may also be fabricated as a P-type device. FIG. 2 is a schematic cross sectional view of a conventional P-type TFET device 200. TFET device 200 (which is very similar to TFET device 100) includes a layer of semiconductor material 202, a source region 204, a drain region 206, and a gate structure 208. In contrast to TFET device 100, however, most of semiconductor material 202 is lightly doped with a P-type impurity (P−), source region 204 is highly doped with an N-type impurity (N+), and drain region 206 is highly doped with a P-type impurity (P+). TFET device 200 includes a channel region 210 that is located between source region 204 and drain region 206.
When used as a semiconductor switch device, TFET device 200 is biased such that Vd is less than Vs. The gate voltage (Vg) is then controlled to turn the switch on or off. More specifically, if Vg is lower than Vt, then the switch turns on and source-to-drain current flows. If, however, Vg is greater than Vt, then the switch remains off. FIG. 2 depicts a state where TFET device 200 is conducting source-to-drain current (Vs=1.0 volts; Vg=0.0 volts; Vd=0.0 volts). Under these bias conditions, holes accumulate in channel region 210 near the upper surface of semiconductor material 202 and directly under gate structure 208. This accumulation of holes in turn creates a very well defined and localized N+/P+ junction between source region 204 and channel region 210. This stiff N+/P+ junction represents a tunneling junction 212 for TFET device 200. Electrons and holes can easily pass or tunnel through tunneling junction 212, which results in high source-to-drain current.